Numerous state retention flip-flop architectures exist. Examples are set forth in: “Data-Retention Flip-Flops For Power-Down Applications”, by Hamid Mahmoodi-Meimand et al., IEEE International Symposium on Circuits and Systems (ISCAS), pages II-677 to II-680, (2004); U.S. Pat. No. 8,253,438, entitled “Low Leakage And Data Retention Circuitry”; and U.S. Patent Publication Number 2011/0298516, entitled “Clock State Independent Retention Master-Slave Flip-Flop.” Retention flip-flops and latches often have an extra balloon latch circuit. The balloon latch circuit stores the logic state of the flop-flop or latch when the flip-flop or latch is in the retention mode. At the end of retention mode operation, when the flip-flop or latch is to operate in the normal active mode again, the logic state information stored in the balloon latch circuit is loaded back into the primary latch of the device. For various reasons, realizing such a retention mode flip-flop or latch generally involves an undesirably large amount of semiconductor die area. Other retention mode devices have been proposed that do not involve extra balloon latches. Examples include devices set forth in: U.S. Pat. No. 7,639,056, entitled “Ultra Low Area Overhead Retention Flip-Flop For Power-Down Applications”; U.S. Patent Publication Number 2011/0248759, entitled “Retention Flip-Flop”; and U.S. Patent Publication Number 2010/0308876, entitled “Semiconductor Integrated Circuit And Method Of Saving And Recovering Internal State Thereof”.